The Signal Gate is the most complex of the Locator circuit boards in both function and assembly. Its purpose is to derive accurate gating pulses, derived from the E-field signals, to capture the peak magnitudes of the pair of magnetic signals, NS and EW, as well as the peak magnitudes of the initial, E1, and first overshoot, E2, of the voltage field signals. The actual peak captures are carried out later by the Track/Hold circuit board.
The Signal Gate function is understood by comparing the circuit schematic to the idealized waveforms map and a few of the actual signals shown in the set of waveform diagrams. For the following discussion, refer only to Part A of the circuit schematic. The filtered E-field signal (A) passes through an optional noise gate analog switch, U1, and then divides between two paths. In most circumstances the noise gate is not required, and so U1 can be replaced with a 100-ohm resistor that mimics U1 in its closed state. One signal path travels via follower U2 and the normally closed analog switch U3 to the 0.001uF capacitor and follower U4. When no valid lightning signal is present, output from U4 is simply low-level noise from the E-field antenna. The other signal path, via a sensitivity trimmer, P1, first encounters an absolute-value circuit around U5 and U6. This circuit converts the input signal of either polarity into a negative-going monophasic signal, (B). This signal again divides between two paths. One path is via Schmitt trigger U7b that generates pulse (C) when the input signal exceeds a threshold set by P3. The leading edge of (C) marks the foot of the input (A) and triggers the enable pulse generator, U8. The enable pulse duration, (D), of about 20 microseconds, establishes a window within which the input wave risetime must fall for an ultimate gate pulse to be created. The 20-microsecond value is somewhat arbitrary and can be shortened substantially, since most lightning signals have risetimes in the range 1 to 5 microseconds. The other path of (B) is via differentiator, U9, to produce a limited first derivative, (E), of the input signal. The initial, rapidly falling limb of (E) crosses zero slightly after the peak of (A) occurs. While, in principle, it should cross zero at the exact moment of the peak, limitations in U9 speed, noise reduction components, and parasitic capacitances all contribute to fractional microsecond delays. As (E) crosses zero, it initiates a second Schmitt trigger, U7a, to create a pulse (F) whose leading edge triggers the gate pulse generator, U10. As long as the leading edge of (F) falls within the duration of the enable pulse (D), U10 will generate the 100-millisecond gate pulse, (G). Pulse (G) is converted by Q1 and Q2 into the required biphasic gate opening pulse, (gop), and then sent on to open the analog switch, U3. Because the leading edge of (gop) opens U3 near the moment of the input wave's peak, the peak value stored in the 0.001uF capacitor holds follower U4 to this value, E1, for the duration (100 milliseconds) of the gate pulse. Pulse (gop) serves a similar function when sent on to the Track/Hold circuit board for capturing NS, EW, and E1 peak signals. A slightly shorter (about 60 to 80 milliseconds) version of gate pulse (G) is developed by U11 as pulse (H). This pulse ultimately reaches the A/D converter to allow it to create a valid signal present logic level for use by the computer software. We have found that more reliable sampling occurs if (H) is slightly shorter in duration than the 100-millisecond captured analog signals.
A few other pulses are derived from the voltage field signal, based on its initial polarity; refer to Part B of the circuit schematic. Pulse (GE) is formed only if the initial polarity of the input wave is positive, thus representing a negative return stroke. This pulse is used by an optional direction-only display. The remaining four pulses are required by the Track/Hold circuit to assist peak detectors (see below) in capturing the peak magnitude and polarity of any E-field overshoot, E2. Pulses (clin) and (clip) are normally (i.e. no signal present) negative. As shown in the idealized waveforms map, close-if-negative (clin)becomes positive if E1 is negative, while close-if-positive (clip)becomes positive if E1 is positive. Similarly, pulses (opin) and (opip) are normally positive. Open-if-negative (opin) becomes negative if E1 is negative, while open-if-positive (opip) becomes negative if E1 is positive. Trim pots P4 and P5 set the thresholds for these pulses to be generated by Schmitt triggers U12a and b accompanied by nand-gate inverters, U13c and d. Transistors Q3 through Q11 establish the proper polarity and biphasic character of these pulses.
A circuit board is available for this Signal Gate from FAR Circuits. See the References section for details. As described for the other boards, first place the jumpers and then the parts on the component side of the board. We suggest that all IC sockets be soldered in place first, taking care to orient properly pins #1 (square pads). Also, with an indelible pen, mark pin #1 of the headers J41, J45, and J47. It is also helpful to label each of the trim pots, P1 through P5. The many jumpers are then installed using bare wire and insulating sleeving. When populating with parts, use care to properly orient the polarized parts (diodes, tantalum capacitors, transistors). Inspect your work frequently and use magnification to discover accidental solder bridges and cold-soldered joints. When all wiring is complete, perform the same static tests as those done on the previous boards. Before any ICs are in place, verify that the +12-volt rail-to-ground resistance is about 23 kohms and that the -12-volt rail-to-ground resistance is about 9 kohms. Currents are about 15 mA in the +12-volt rail and 11 mA in the -12-volt rail. After installing all ICs, note that the rail-to-ground resistance is unchanged, but that +12-volt current rises to about 140 mA and -12-volt current rises to 55 mA. If these currents are obtained and each component is getting no more than slightly warm, then proceed to the final testing.
Adjust trim pot P1 to its fully clockwise position (100%). With the aid of a voltmeter, adjust the remaining four trim pots so that the levels shown on Part A of the schematic appear at each pot rotor (center terminal). Connect the Antenna Simulator or the newer Lightning Stroke Simulator E-Out to the Filters input (J24I) and the Filters output (J24O) to the Signal Gate input (J44). Set the Simulators for 1 Hz, mono (Antenna Simulator) or Rtrn (Lightning Stroke Simulator), norm, and max (2.5 volts) output. The Simulator NS and EW outputs are not used at this time.
With an oscilloscope adjusted for a sweep of about 2.5 microseconds per major division and a vertical sensitivity of about 1 volt per major division, look for the familiar waveform at (A) on the center pin of J44. If the newer Lightning Stroke Simulator is used in place of the older Antenna Array Signal Simulator, then all the following waveforms will have a slightly different appearance. See Figure wvee.jpg of the Lightning Stroke Simulator section. This will assure that the board is receiving an appropriate test input signal. If a second 'scope channel is available, then set its vertical sensitivity to the same 1 volt/division, and connect its probe to (B), pin #6 of U6, and find the waveform shown on CH2. If only a single 'scope channel is available, then connect it to (B) to discover this signal appearance. Next, temporarily switch the Simulator to Biphasic (IntCld) output and find that the waveform at (B) now appears. An alternative test of the proper performance of the absolute value circuit at (B) is to simply switch the Simulator output between norm and inv (Norm and Invrt) in either the mono (Rtrn) or Biphasic (IntCld) mode and note that there is no change in (B). If similar signals are not found at (B) when (A) appears normal, then find and correct any component or wiring fault before proceeding further.
Reset the Simulator for norm and mono (Norm and Rtrn) output for the remaining tests; refer to Part A of the circuit schematic. Proper functioning of the Schmitt trigger, U7, is confirmed by finding the waveforms at (A) and (C), U7b--pin #7, while proper functioning of the enable pulse generator, U8, is confirmed by finding the waveforms at (A) and (D), U8--pin #6. Trim pot P3 sets the threshold for enable triggering; if set too low, then enabling occurs from noise or prematurely from stepped leaders in lightning. The optimum P3 setting is in the range of -0.1 to -0.2 volts in the prototype units. Differentiator function of U9 is found at (E), U9--pin #6, by finding the waveform at (E), with the rapidly descending signal that crosses zero just after the input wave (A) peak. Adjusting P2 can bring the moment of zero crossing closer to the peak, but such timing is slightly dependent on the input signal magnitude. With P2 set for 0 volts, the crossing is 0.3 to 0.4 microseconds after the peak. Optimum setting of P2 for capture of the slightly delayed magnetic signal peaks (due to the Antenna Array circuits) may require P2 to be advanced to a slightly positive voltage (0 to 0.050 volts). Proper function of Schmitt trigger U7a and gate pulse generator U10 is found at U10--pin # 6 by showing a sharp rise at the moment of (E) zero crossing and remaining high for about 100 milliseconds as seen by the waveform at (G). Attempting to observe the signal (F) at U7a--pin #12 is unsatisfactory, as the capacitance loading of the 'scope probe introduces instability and erratic signals. The biphasic version of the gate pulse, (gop), is found at analog switch U3--pin #6. The waveform at (gop) should appear as a normally +5-volt level that rapidly changes to -5 volts just after the input wave peak, which appears as the vertical line at (A) due to the much slower 'scope sweep. Proper capture of near-peak-magnitude and polarity of the input (A) is ensured by finding the waveform at (E1). Changing the Simulator output to inv (Invrt) should invert both (A) and (E1); likewise switching the Simulator output from max (2.5 volts) to min (1 volt) should show appropriate magnitude changes in both (A) and (E1). The remaining pulses, (H), (GE), (clin), (opin), (clip), and (opip), are generated by simple, rugged circuits that should pose no problem unless gross faults have occurred. They may be checked using the same procedures as those above by comparing 'scope images at the points shown on the circuit diagram with the waveforms map.
Positive and negative threshold pots, P4 and P5, respectively, for initiating the pulses derived from the polarity of E1 may be set to the levels shown on Part B of the circuit diagram. Their exact settings are not critical.
When all the above tests are successful, the Signal Gate board can be installed in the Interface cabinet and is ready to interface with the Track/Hold board, the next item to be built.