Monophasic (Rtrn) input signal from the Simulator at point (A) on the Signal Gate circuit diagram and gate pulse generated by U10 of about 110 milliseconds duration, (G). Its leading edge slightly lags, by about 0.4 microseconds, the peak of the input signal. The duration of (G) establishes the duration that the input peak magnitude is held (stretched).  Note the much greater time period of 25 milliseconds per cm along the abscissa.