Logic offers complementary-switch control

Edited by Bill Travis

Yen-Hsu Chen, Analog Integrations Corp, Hsinchu, Taiwan -- EDN, 12/6/2001

The complementary-switch controller in Figure 1 uses a few inverter gates to provide drive signals for the complementary switches. Complementary-switch configurations find widespread use in synchronous-rectification circuits, charge pumps, full-bridge control circuits, and other circuits. The circuit in Figure 1 provides not only a complementary drive signal but also a deadtime delay on both rising and falling edges. The high-speed inverter gates use IC₁, a 74HC04 CMOS circuit, and 1N5819 Schottky diodes D₁ and D₂. The 74HC04 inverter features symmetrical input thresholds, V_IHMIN and V_ILMAX, at 70 and 30% of the supply voltage, respectively. In Figure 1, IC_1A inverts the signal at Node A to produce . When  rises, C₁ rapidly charges through D₁. Output B drops immediately because of IC_1B's inversion. However, Output C drops after a delay time that R₂ and C₂ determine because D₂ is reverse-biased. The following formula gives the delay time, t₁ (Figure 2):

When  falls, C₁ discharges through R₁. Output B rises after a delay time that R₁ and C₁ determine. C₂ discharges rapidly through D₂, and output C rises immediately. The following formula gives the delay time, t₂:

By inverting C, IC_1D can provide a signal with the same polarity as B. By selecting values for R₁, C₁, R₂, and C₂, you can program the delay times. The delay can be as short as 50 nsec and as long as several milliseconds. This range provides flexible, optimized control for target devices. R₁ and R₂ should be larger than 2 kΩ because of the limited current available from the inverter IC.

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