Circuit allows high-speed clock multiplication

Edited by Bill Travis

Lukasz Sliwczynski and Przemyslaw Krehlik, University of Mining and Metallurgy, Krakow, Poland -- EDN, 5/2/2002

In theory, synchronous clock multiplication is an easy task. A simple PLL with two digital dividers—one inserted just after the VCO (voltage-controlled oscillator) and the second one placed directly at the input of the phase detector—may do the job. The flexibility of such a configuration allows for clock multiplication by any rational number. However, a problem emerges if you want to multiply a high-frequency clock. Standard, integrated PLLs, such as the 74HC/HCT4046 and NE564, do not accommodate such fast clock signals; they're limited to frequencies lower than approximately 60 MHz for the NE564. Although you can implement almost all PLL subcircuits by using fast programmable logic, such as CPLD or FPGA circuits from Xilinx (www.xilinx.com), a big problem exists in providing the proper high-frequency VCO. Two obvious possibilities exist: Order the VCO from a company specializing in high-frequency circuits, or build it yourself. The first approach can be costly; the second requires specialized knowledge and can be frustrating for an inexperienced designer. The circuit in Figure 1 offers yet another possibility.

The circuit is based on IC₁, Gennum Corp's (www.gennum.com) GS9015A clock-recovery IC, an ECL-based circuit that can operate at frequencies to approximately 400 MHz. You normally use such an IC to extract clock information from a digital NRZ data stream with the aid of an input divider. The clock-recovery circuitry is in principle a form of PLL with a special type of digital phase comparator. The comparator allows for VCO phase adjustment only when high-to-low or low-to-high transitions are present in the input signal. This property of the clock-recovery circuit allows you to exploit it as a clock multiplier. If you apply a signal with 50% duty cycle instead of a normal NRZ data stream to the input of the clock-recovery circuit, the circuit attempts to interpret the signal as a sequence of N consecutive zero and one symbols and controls its VCO in such a way as to produce a clock transition for each symbol. The result is a multiplication of the input frequency by the factor 2N. You set the actual multiplication coefficient by setting the VCO's free-run frequency close to the desired output clock frequency. To avoid locking of the clock-recovery circuit to some undesired multiplication coefficient, you should make the VCO's tuning range narrow.

This design is applied to a 4B5B encoder, which needs to derive a 125-MHz clock from a 100-MHz master-clock signal; therefore, it needs a multiplication factor of 5/4. To realize this operation, you must first divide the 100-MHz clock by 8 and then multiply the result by 10. (Note that only even multiplication coefficients are possible using the concepts in this Design Idea.) Figure 2 shows some key waveforms the circuit produces. The complete design implements the remaining part of the encoder with IC₂, a 3.3V XC9572XL CPLD IC to match logic levels. Resistor R₃ and capacitors C₃ and C₄ form the loop filter, and resistors R₄ and R₅ set the free-run frequency of the VCO. The circuit in Figure 1 is simple and easy to build. The only trimming it requires is the initial setting of the VCO's free-run frequency (close to 125 MHz). You perform this trim by observing the output waveform with an oscilloscope and adjusting variable resistor R₅ with R₂ shorted.

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