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Circuit divides frequency by N+1
Edited by Bill Travis
Bert Erickson, Fayetteville, NY -- EDN, 7/11/2002
Digital frequency dividers usually use flip-flop stages
that connect the  pin to the D data-input pin of the following stage. This configuration creates a binary waveform that you can feed back to the input. You can divide any integer lower than 2N
with minimal stages, where N is the number of stages. These dividers can easily select one frequency from 100 for a receiver. However, as the applied clock rate approaches the ratings of the devices, decoding spikes appear. As a result, you'd be ill-advised to use the dominant pulse in such a waveform for clocks or strobes. The divider in Figure 1 uses a ring
configuration, and the stages connect Q-to-D, without using the
output, to provide a binary sequence. Consequently, the circuit can divide only by N+1, but it produces a clean waveform at an applied clock rate that's substantially higher than you can apply to conventional binary dividers using flip-flops from the same process families.
If the last Q in a cascade of 74xx174 flip-flops connects to the D input, the loop becomes a shift-register ring counter. Moreover, the circuit can operate at a clock rate higher than that of any other configuration. Unfortunately, when you turn on the power or ground the reset pin, all Q outputs go low and remain low when you apply the clock. To circumvent installing a preset circuit that must operate at a high clock rate, you can place one NOR gate with its propagation delay in the loop. This addition ensures that the divider always starts and continues to function properly. Because this gate receives inputs from all stages at once, it features parallel carry and has the properties of a parallel-carry counter. For simplicity, Figure 1 does not show the reset line, and you can delete the broken feedback lines, providing that you ground the corresponding input pins. You can take the output from any Q pin and use an additional stage, such as Q5, for a buffer. Although the output of the NOR gate resembles one of the Qs, you should not use it as an output.
Figure 2 shows the timing diagram for the divider. Section A of the diagram shows the state of D0 and the Q outputs in the start-up condition before the first and second clock pulses arrive. Note that when the power turns on or when the reset pin connects to ground, the Q outputs are all low, and D0 is high. D0 then transfers to Q0 on the rising edge of the first clock pulse. Section B of the diagram shows the output for a repetitive sequence starting with Q0. Section C is an expanded representation of the end of the sequence. Note that Q2 falls after the clock pulse rises. Then, with all Q outputs low, D0 rises a short time later to allow the sequence to repeat. D0's transfer can take place only after the next clock pulse rises. This factor creates an additional time slot to make the total N+1. Section C shows the propagation delay attributable to the NOR gate—approximately 10 nsec for most logic-circuit families and less than 5 nsec for the F and S series. This propagation delay is the only additional delay in the loop. A comparison of the output waveforms with those from a 74xx90 divide-by-5 counter shows prominent decoding spikes from this counter. The N+1 divider had no spikes and operates at a much faster clock rate.
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