Design Ideas February 17, 1997

ISA bus provides access to serial peripherals

Jerzy Chrzaszcz, Warsaw University of Technology, Warsaw, Poland

Designers often switch from parallel to serial data-interface configurations to save pins and shrink IC packages. A serial interface consists of one bidirectional data line, a clock line, and--sometimes--additional control lines or lines that organize data transfers. You can easily connect peripherals with serial interface to the ISA bus through an I/O port that latches control and data bits. By sending appropriate bit patterns to such a port, you can set data and control lines and toggle the clock to send information to and receive information from the peripheral bit by bit. This approach is straightforward but may bring some complications in the control program. Its main disadvantage is substantial overhead: To transfer one data byte, you need at least eight clock cycles, which are generally slow on the ISA bus. If you cannot accept such delays in your system, you might find the interface circuit in Figure 1 useful.

The circuit offers parallel read and write; byte transfer thus requires just one I/O bus cycle instead of eight. All operations necessary to exchange serial data with the peripheral occur autonomously and transparently. The interface consists of a GAL22V10 PLD that integrates a state machine and some combinatorial logic and a 74LS322 multimode register connected to the data bus. The register's serial output connects to the serial input via a tristate buffer, thus allowing bidirectional operation. The clock signal for the register and the peripheral comes from the bus clock, gated and inverted in the PLD. The state machine's outputs directly control the CS, RE, and LE lines. Listing 1 gives the pin definitions and logic equations for the PLD.

Click here to download this listing and others pertaining to the PLD, including a CUPL-simulation routine, from file DI-SIG, #1989. The data-read operation cycles through the IDLE-MOVE-DONE-IDLE path in Listing 1; the data-write routine cycles through the IDLE-LOAD-MOVE-IDLE path. On data read, asserting IOCHRDY low suspends the bus cycle, provided new data bits shift from the peripheral into the register.

After eight clocks, IOCHRDY becomes negated, and the bus cycle finishes. On data write, the register loads with parallel data, the bus cycle completes normally, and then the data byte shifts from the interface register to the peripheral. The state machine safely recovers from some potentially hazardous contexts (such as write immediately followed by read). You can easily adapt the proposed interface for specific requirements by changing the control signals' sequence or polarities. Although Figure 1 shows a 22V10 PLD, the control logic also accommodates 20G10 devices. (DI #1989)