While the Track/Hold circuit board is rather crowded with many components and a great many component-side jumpers, its function is not very complex. It simply captures the peak magnitudes of the four signals, E1, E2, NS and EW and sends them on to the A/D converter as 100 millisecond-duration pulses of proportional magnitude. All the critical timing and generation of gate pulses, used by the Track/Hold circuits, has been accomplished by the Signal Gate board.
Capture of the NS and EW peaks is carried out in the identical manner as that done for E1 in the Signal Gate board (see idealized waveform map and Signal Gate circuit diagram). NS and EW peak signals at J52 and J53 are connected each to 0.0027uF capacitors through a pair of normally closed analog switches in U1. The potentials present on these capacitors are that of background noise from the Antenna Array and drive voltage followers, U2 and U5, and the 2.5-volt offset circuits around U3-U4 and U6-U7, respectively. (The U2 to U4 and U5 to U7 circuits are identical to those shown for U11 to U13 in Part B of the circuit diagram). When the Signal Gate board detects a lightning signal, it generates the gate opening pulse, (gop), that opens the analog switches, U1, at the moment of the signal peak. Analog switch opening leaves the peak magnitudes on the capacitors for the 100-millisecond duration of (gop) and appears at the voltage follower outputs.
The initial peak of the E-field signal, E1, is captured in the same manner as described above. The E-field signal at J54, (A), is supplied to a 0.001uF capacitor via voltage follower U8 and one normally closed analog switch within U9. When gate opening pulse (gop) opens the analog switch, the peak magnitude of the E-field signal is left on the capacitor and appears as the output of follower U11, (E1)). The 2.5-volt offset, required for the A/D converter, is carried out by U12 and U13 (also U3-U4 and U6-U7 for the NS and EW signals, above) and these offset signals are shown as initiated by the Simulator in the norm (Norm) and inv (Invrt) settings.
Capture of the E-field overshoot peak, E2, uses a pair of gated peak detectors, one to capture negative overshoot peaks, U10-Q1, and the other to capture positive overshoot peaks, U15-Q2. Comparing the idealized waveform map to the Track/Hold circuit diagram and the Signal Gate circuit diagram may be helpful here. The E-field signal from follower U8 connects to each peak detector through normally open analog switches in U9 and U14. If the Signal Gate board detects that the initial polarity of the E-field signal is positive (i.e. E1 is positive), then its overshoot must be negative. It, therefore, generates the close-if-positive, (clip), pulse that connects the E-field signal from U8 to the negative peak detector, U10-Q1, via one switch in U9 and a follower 0.0033uF capacitor to the detector output through another switch in U9. Simultaneously, the Signal Gate board generates an open-if-positive, (opip), pulse that removes the short across the capacitor via the fourth switch in U9. The peak detector then captures the negative going maximum excursion of the E-field overshoot and sends it on to follower U16. If, however, the initial polarity of the E-field signal is negative (E1 is negative), and hence has a positive polarity E2, then the Signal Gate board generates the close-if-negative, (clin), and open-if-negative, (opin), pulse pair. In a similar manner to that above, the E-field signal is connected to the positive peak detector, U15-Q2, and its output is connected to the second 0.0033uF capacitor and follower U17. The two follower outputs are then combined in U18 and are offset 2.5 volts by U19.
A circuit board is available for this Track/Hold from FAR Circuits. See the References section for details. The first set of jumper wires is installed and the parts are placed on the component side of the circuit board, as done for previous boards. All IC sockets should be soldered in place first, taking care to orient pins #1 (square pads) properly. Also, with an indelible pen, mark pin #1 of the headers J51, J56, J57 and J58. When populating with parts, use care in proper orientation of polarized parts (regulator ICs, tantalum capacitors, transistors). Inspect your work frequently and use magnification to discover accidental solder bridges and cold-soldered joints. When all electronic components are installed, add the second set of jumpers. As a final wiring step, add two pairs of 2-1/2 inch lengths of small insulated solid wire (#24 is ideal) to the pads near U1, as shown in the parts placement diagram, on the solder side of the circuit board to form gimmick capacitors, C1 and C2. Their adjustment is discussed below. (Caution: the solder side is a mirror image of that seen in the parts placement diagram.) When all wiring is complete, carry out the same static tests as done on previous boards. Before any ICs are in place, the +12 volt rail-to-ground resistance should exceed 3meg and the -12 volt rail-to-ground should be about 28k. Currents are about 6 mA in each rail. After all the ICs are installed, rail-to-ground resistance is unchanged, but the +12 volt current rises to about 100 mA and the -12 volt current rises to 70 mA. If close to these currents are obtained and the components are getting no more than slightly warm, then the circuit board can be installed in the Interface Cabinet, all cables connected, and the final adjustments and testing performed.
The small amount of gate pulse cross talk at U1 is neutralized with the "gimmick" capacitors, C1 and C2, installed as short insulated wire pairs on the solder side of the circuit board, above. As shown in the interconnections diagram, connect the Simulator to the Interface with the E-field out to J14, NS out to J12, and EW out to J13 to provide filtered test signals to the Signal Gate board and the Track/Hold board. Set the Simulator to mono (Rtrn), norm (Norm), max (2.5 volts), and both NS out and EW out to off (center-off switch positions) (be sure to disconnect NS and EW from the Antenna Stroke Simulator). With an oscilloscope triggered from the Simulator Synch Out jack (Note: there is no Synch Out jack on the Lightning Stroke Simulator. Trigger the oscilloscope from the E-Field input jack on the Interface), set its sweep to about 50 milliseconds per cm and vertical sensitivity to about 20 millivolts per cm. Connect the oscilloscope probe to pin #6 of U5 and observe a small, negative-going, 100-millisecond pulse as shown on Channel 1 of the gate neutralization figure. The signal may be rather noisy but the pulse should still be visible. Tightly twist together the wire pair from the pad near U1, pin #4, and the pad near J57, pin #4 (G), over a length of about 1-1/2 inches. Again, observe the 'scope waveform that should look more like a straight line as seen in Channel 2 of the gate neutralization figure, which shows proper neutralization. If there is still some negative excursion present, then add another twist or two, or, if the excursion is now slightly positive, then remove a twist or two. Add or remove twists until the best straight-line trace is obtained, showing that neutralization is optimum. Repeat the above for the EW channel by twisting the remaining pair from the pad connected to U1, pins #9, 11, and the pad near J57, pin #4, to achieve a 'scope trace as in Channel 2 of the gate neutralization figure. Any remaining lengths of untwisted wire should be clipped off. This completes the cross-talk neutralization and is the only adjustment that is made on this circuit board.
Proper performance of the Track/Hold circuit board is confirmed by obtaining the signal waveshapes described earlier and shown in the cases of NS in/out, E1 output at U11, normal E1 offset output at U13, inverted E1 offset output at U13, negative E2 output at U16, and positive E2 output at U17 when the Interface is driven by the Simulator, and in the case of NS output at U2 when the Interface is driven from the Antenna Array and the Test Signal Source. The final test, with a signal through the Antenna Array, reveals that the fractional-microsecond NS and EW channel delays allow capture of the true peaks of this signal pair. Accurate capture of these signals is critical to bearing and distance location. A similar degree of accuracy is not required of E1 and E2, as only their approximate ratio is used to distinguish intracloud from return strokes, and the E1 polarity used to separate positive from negative strokes.