Crystal Set Diode Detector Power Loss, with Current and Voltage Waveforms as determined 
from SPICE Simulation.

By Ben H. Tongue

Quick summary:  This Article shows diode detector voltage and current waveforms and how they change as a function of signal strength.

In this article I am going to show an analysis of the operation of a crystal set detector using a SPICE simulator.  The detector voltage and current waveforms will be shown for three different input "available power" sources.  These sources will supply either  -85.54, -65.54 or -45.54 dBW (number of dB's below one Watt) power to a matched load.  Each power source is made up of a pure voltage source combined with a resistance.  (The combo could also be referred to as a "voltage source with an internal resistance").  In each case the available input power, the output power and detector insertion loss will be shown. Conformance to or deviation from the usually assumed peak-detector model will be investigated.  The change in input resistance with change in input power will also be examined.

Here is a derivation one needs to know in order to understand the rest of this article.  The concept of "available power":  If one has a voltage source V with an internal resistance R, then the load resistance to which the maximum amount of power (Pa) can be delivered is itself equal to R.  Pa will be called the "maximum available power".  Any load resistance other than one equal to the source resistance R will absorb less power from the source.  This applies whether the voltage is DC or AC (RMS).  An equation for power absorbed in a resistance is voltage squared divided by resistance.  In the impedance matched condition, because of the 2 to 1 voltage division from the source resistance and load resistance, one-half of the internal voltage V will appear across the load resistance.  The actual power absorbed by the load will be, as indicated in the preceding relation: P = ((V/2)^2)/R = (V^2)/(4R).  Half of the power delivered to the series combination of the source resistance and the load resistance will be delivered to the load.  The other half is dissipated and lost in the source resistance.  In the crystal radio case the input voltage is AC RF voltage.  If the input voltage is referred to by its peak value (Vp) as it is in SPICE, instead of by its RMS value, the equation changes.  The RMS voltage of a sine wave is equal to the peak value of that wave divided by the square root of 2.  Since the power equation squares the voltage, the equation for the "available input power" changes to P = (Vp^2)/(8R).  This is the equation that will be used to calculate available input power to the detector, from the source.

Here are some definitions, assumptions and explanations:

1. The internal resistance of the antenna is transformed up to the equivalent parallel resistance R that is used in the simulation.  The tuned circuitry used to do this is not shown.
2. The single tuned circuit used is assumed to have an infinite Q.  A finite Q will cause an increase in insertion loss.
3. "Diode Detector Power Loss" is defined as the ratio of DC output power dissipated in the output load resistance to the RF input "available power". (Expressed in dB)
4. The L/C ratio of the tuned circuit L1, C1 is sufficiently low so that no appreciable harmonic voltages will be developed across it by the detection action of the diode.
5. The RF bypass capacitor C2 is sufficiently large so that the RF ripple voltage across it is small compared to the voltage across the tank circuit. (Appreciably all to the tank circuit voltage, therefore, appears across the diode).
6. The output load resistance may seem to be a high value for headphones.  It is assumed that in practice, the headphone impedance will be transformed up to that value by a low loss audio transformer.  It is also assumed that the transformer primary has an appropriate capacitor bypassed resistor in series with it.  The purpose of this is to insure that the audio load on the diode has the same DC as AC value.
7. The RF and AF load resistances used in the simulation will seem quite high.  This is because the average unloaded shunt resistance of the loop in my single tuned loop receiver is 700k Ohms, and I am using it in the simulation that follows.
8. The diode junction capacitance is set to zero in the netlist.  This has no effect on the operation of the detector if C1 is retuned to take account of this fact.  Experimentation is now more convenient since a change of C2 will have no effect on tuning.
9. The diode parameters are specified so as to produce an RF input resistance of 700k Ohms when operated in a detector circuit and driven by a low available power source of, say, -85 dBW.

A basic crystal set diode detector schematic is shown below.  An Intusoft SPICE simulator will be used in three separate simulations to measure circuit currents and voltages.  The calculations from the simulations will show that the detector insertion loss approaches zero at high input power levels and that it goes up sharply as the input power goes down below a certain point.  This loss will be minimized if the input and output resistances of the detector are impedance matched.  The following discussion assumes that the RF source and both the DC and Audio AC load are matched to the diode at a low signal input power level.  Two modes of operation for a detector have been defined:  Linear and square law.  Linear operation is said to occur when a change of input power (in dB) causes an equal change in output power.  Square law operation is said to occur when a given small change in input power (in dB) causes double that change in output power.  Where is the breakpoint between linear and square law operation?  SPICE simulation gives the answer, to the extent that SPICE and the diode models are accurate (See Note 1. after SPICE netlist).  An input power sufficient to cause the rectified DC current to equal to the saturation current (Is) of the diode is an indication of operation half way between linear and square law.  The detector power loss at this level is 7.1 dB.
 
 

The Intusoft ISpice netlist shown below is automatically generated by the SpiceNet program after the schematic and parts values are entered into the program.

C:\spice8d\Circuits\XSchottky.cir Setup1
*#save V(1) V(2) @R1[i] @R1[p] @C1[i] @L1[i] V(3) @D1[id]
*#save @D1[p] @C2[i] @R2[i] @R2[p]
*#viewtran iy3
*#alias iy3 @d1[id]
*#alias y1v(1)
*#viewtran y1
*#alias y2v(2)
*#viewtran y2
*#alias y3xv(3)
*#viewtran y3x
.TRAN 31.25n 502u
*#save all
.OPTIONS reltol=0.00001
.OPTIONS vscale=0.25
.PRINTTRAN IY3
.PRINTTRAN Y1
.PRINTTRAN Y2
.PRINTTRAN Y3x
V1 1 0 SIN 0 0.125 1meg 0 0 0
R1 1 2 700k
C1 2 0 50.52p
L1 2 0 500u
D1 2 3 _HP2835
.MODEL _HP2835 D BV=15 CJO=0 EG=0.69 IBV=2.5e-5 IS=38nA
+ N=1.03 RS=6.4 VJ=0.56
C2 3 0 100p
R2 3 0 700k
END

Note 1:  In regard to the accuracy of the SPICE diode model, some diodes, notably the 1N34A are unusual.  The values of Is and n are not constant and do vary with diode current.  Measurements made on one 1N34A shows Is and n values of 2.7E-6 and 1.64 at 320 uA which drop to 1.21E-6 and 1.34 at 32 uA, then down to 6.6E-7 and 1.05 at 1.8 uA.  Schottky diodes seem to have constant values for n and Is.
The SPICE netlist above shows, as the input, a 1.0 MHz sine wave of peak amplitude 0.125 volts for V1. (This Input signal level is 2.74 dB less one that would operate the detector half way between the linear and square law modes. At this lower input signal power level the insertion power loss of the detector is 7.12 dB).  The first of the three simulations will be done with an input sine wave of 0.125 volts peak for V1 as shown in the netlist.  The second simulation will use a 1.25-volt peak sine wave. The third will use a 12.5-volt peak sine wave.  The respective available input powers are: -85.54 dBW, -65.54 dBW and -45.54 dBW (dB below one Watt).
 
 

The black curve shows the diode current.  The other three curves all use the same scale on the vertical axis.  The blue curve shows the voltage at the test point Y2.  This is the voltage across the tuned circuit.  It has a peak value of 61.9 millivolts, about 1/2 that at test point V1.  This shows that the detector has an input resistance of about 700k Ohms.  There is a good input impedance match here.  The red curve shows the voltage across the diode.  Note that where it is positive, a forward diode current flows for about 42% of the time for one cycle of the 1.0 MHz wave.  Note that where it is negative, a reverse diode current flows. This reverse current flattens out and if a higher input signal was used, it would flatten out at about 38 nanoAmps, the saturation current of the diode.  Finally, note that there is no peak detection going on.  The diode output voltage, measured at test point Y3x is only 15.7 millivolts even though the peak forward voltage applied to the diode is 61.9 millivolts.  Input power as stated above is -85.54 dBW. The output power is ((0.0157)^2)/700k = -94.53 dBW.  Insertion loss = 94.53 - 85.54 = 8.99 dB.
 
 

Here, the input voltage at test point Y1 is 1.25 volts, but the voltage across the LC tank circuit, as measured at test point Y2 is only 494 millivolts, not 625 which would be the case if we had a perfect impedance match.  This shows that the detector input resistance is now lower than 700k Ohms.  Diode operation is getting closer to peak detection. The green output voltage at test point Y3x is 361 millivolts.  Forward current is now drawn over about 24% of one cycle time.  The input available power, as stated
Before, is -65.54 dBW.  The output power is ((0.361)^2)/700k = -67.30 dBW.  Detector power loss is: 67.30 - 65.54 = 1.76 dB.
 
 

Now it looks as if we are getting much closer to peak detection.  The peak positive voltage applied to the diode at test point Y2 is 4.30 volts.  The detected DC voltage at test point Y3x is 4.08 volts (only about 5% less than the 4.30 volt peak).  The diode forward conducts only during 12% of the cycle time of the 1.0 MHz wave.  As stated before, the input available power is -45.54 dBW.  The output power calculates as: ((4.08)^2)/700k = -46.23 dBW.  Detector power loss goes down to: 46.23  45.54 = 0.69 dB.  The input resistance is now even lower than before.
The green output voltage at test point Y3x is 4.08 volts, kind of low compared with the 6.25 volts we would get with a perfect input impedance match.  Why is this?  The input and output resistances of a diode detector both approach the value (0.026*n)/Is Ohms at low signal power levels. (n and Is are diode parameters used in SPICE.  n is called the diode Ideality Factor, or Emission Coefficient.  Is is called diode saturation current.)  Is is defined as the current that is asymptotically approached in the diode back bias direction before extraneous leakage factors or reverse breakdown comes into play.  It also has a major effect at an on the amount of current a diode will pass in the forward direction at any specific applied Voltage.

As we have seen, as signal input power increases, the quality of the RF impedance match starts to degrade.  The input resistance to the diode detector decreases from the value obtained in the first well matched low power level simulation.  Interestingly, the output resistance increases. The reason for this change is that a new law now governs input and output resistance when a diode detector is operated at a high enough power level to result in a low power loss.  The rule here is that the input resistance of a diode peak detector is ½ the value of the output load resistance.  Also, the output resistance is equal to 2 times the value of the input source resistance.  Further, since the detector is a peak detector, the DC output voltage is the square root of 2 greater than the input RMS voltage.  This relationship is necessary so that in an ideal peak detector, the input power will equal the output power (No free lunch).  If we were to adjust the input source resistance to, say 495k Ohms and the output load resistance to 990k Ohms (by changing the input and output impedance transformation ratios), the power loss would be even lower than 0.69 dB and the input and output impedance matches would be much improved.

Published: 02/13/00;  Last revision: 04/14/01