To perform the simple arithmetic required, DSP processors need special high speed arithmetic units.
Most
DSP operations require additions and multiplications
together. So DSP processors usually have hardware adders and multipliers which
can be used in parallel within a single instruction:
The diagram shows the data path for the Lucent DSP32C processor. The hardware multiply and add work in parallel so that in the space of a single instruction, both an add and a multiply can be completed.
Delays require that intermediate values be held for later
use. This may also be a requirement, for example, when keeping a running total
- the total can be kept within the processor to avoid wasting repeated reads
from and writes to memory. For this reason DSP processors have lots of
registers which can be used to hold intermediate
values:
Registers may be fixed point or floating point format.
Array handling requires that data can be fetched efficiently
from consecutive memory locations. This involves generating the next required
memory address. For this reason DSP processors have address
registers which are used to hold addresses and can be used to generate
the next needed address efficiently:
The ability to generate new addresses efficiently is a characteristic feature of DSP processors. Usually, the next needed address can be generated during the data fetch or store operation, and with no overhead. DSP processors have rich sets of address generation operations:
| *rP | register indirect | read the data pointed to by the address in register rP |
| *rP++ | postincrement | having read the data, postincrement the address pointer to point to the next value in the array |
| *rP-- | postdecrement | having read the data, postdecrement the address pointer to point to the previous value in the array |
| *rP++rI | register postincrement | having read the data, postincrement the address pointer by the amount held in register rI to point to rI values further down the array |
| *rP++rIr | bit reversed | having read the data, postincrement the address pointer to point to the next value in the array, as if the address bits were in bit reversed order |
The table shows some addressing modes for the Lucent DSP32C processor. The assembler syntax is very similar to C language. Whenever an operand is fetched from memory using register indirect addressing, the address register can be incremented to point to the next needed value in the array. This address increment is free - there is no overhead involved in the address calculation - and in the case of the Lucent DSP32C processor up to three such addresses may be generated in each single instruction. Address generation is an important factor in the speed of DSP processors at their specialised operations.
The last addressing mode - bit reversed - shows how specialised DSP processors can be. Bit reversed addressing arises when a table of values has to be reordered by reversing the order of the address bits:
- reverse the order of the bits in each address
- shuffle the data so that the new, bit reversed, addresses are in ascending order
This operation is required in the Fast Fourier Transform - and just about nowhere else. So one can see that DSP processors are designed specifically to calculate the Fast Fourier Transform efficiently.
