RELEASE NOTES FOR SNAPSHOT 20010930

A Mac OS X port has been contributed by Timothy Wood. See the
README.txt file and the macosx.txt files.

The Cygwin port has been repaired by Venkat Iyer. I've been keeping
the mingw port up to date, but this led to some problems with the
Cygwin port. Also, the Cygwin tools have been improving. So Venkat has
fixed up the port for the latest cygwin tools.

The ivl_target API gained the means to access attributes attached to
logic devices in the Verilog source. This supports the $attribute
syntax. This new ivl_target support allows the fpga target to generate
certain platform specific devices.

The FPGA target also now supports PAD attributes. This allows the
programmer to assign ports of the root module to pads of the
device. The feature uses the port direction to know what kind of PAD
to generate, and emits the necessary EDIF to get it to work. You can
assign signals to specific pins, or let P&R choose pins for you. The
virtex code generator emits the I/OBUFS needed. See the fpga.txt
file.

When generating Virtex code, the fpga code generator emits proper
carry chain logic for efficient implementations of wide addition, and
also uses carry logic for fast identity compares.

Stephan Boettcher contributed code to improve the quality of the VCD
output. In certain cases, this change causes *vast* reduction in the
size of the vcd output. It's even performed better then Verilog XL in
certain tests:-)

A bunch of bugs have been fixed, including some == expression width
mismatches, Unary - in behavioral code with the vvp backend, short
l-values when the r-value is a concatenation, assignment to
out-of-bound address of memory.