Design Feature: March 31, 1994

In the early 1980s, slow CPUs were the limiting factor to system processing; peripherals and memory interfaces were faster. But since the mid-1980s, all that has flip-flopped: Now, the bottleneck for transferring data has shifted from CPUs to I/O devices. Today, CPUs typically run at 50 MHz and fasterÑspeeds that strain or exceed the capacity of communication pathways to memory and I/O devices. As a result, system designers trying to match CPU speeds are looking toward high-speed serial buses to extend computer memory and I/O bandwidths.

To extend the bandwidth of parallel buses, designers must increase clock rates and widen data paths. However, these solutions entail high power consumption, increased real estate, high cost, increased crosstalk, and decreased noise immunity due to skew factors and the large-ground-bounce effects of many lines switching at once. A high-speed serial bus transmits data over a single path, which eliminates many of these potential problems, providing that the electrical connection can handle the fast data rates.

One way designers are increasing memory and I/O bandwidth is by using the AutoBahnÑthe VMEbus's answer to high-speed serial communications. PEP Modular Computers created the AutoBahn for 3U VMEbus cards. The AutoBahn uses two little-used lines on the P1 connector, B21 and B22, defined as a serial clock and a serial data line for low-speed communications. AutoBahn develops a differential 50 Ohm transmission line on these two lines to transfer data initially at 200 Mbytes/sec (1.6 Gbps) using positive-ECL-compatible (PECL) transceivers. In the future, transfer rates will reach 400 Mbytes/sec (3.2 Gbps).

AutoBahn is part of the VMEbus extension, which also adds VME64 and source-synchronized block-transfer (SSBLT) capability to an IEEE-1014-compatible VMEbus. In February 1993, several companies, including Motorola Semiconductor, formed the AutoBahn Consortium to develop an ECL gate array, called the Spanceiver (serial-parallel transceiver) to transfer data over AutoBahn. The Spanceiver employs Motorola's Mosaic V ECL-in-Picoseconds-Lite technology.

The Spanceiver has a 16- or a 32-bit TTL parallel interface, which the chip serializes for transmission at PECL levels. The same single-chip Spanceiver, on other boards in the same backplane converts the serial data back into 16- or 32-bit parallel data for the receiving board. The chip inserts a synchronization bit, which guarantees a transition at the start of each transmitted byte. An on-chip phase-locked loop, which employs an off-chip crystal reference, detects the synchronization bit to maintain timing accuracies.

VMEbus performs arbitration

The AutoBahn employs the VMEbus arbitration and data-transfer buses to control the flow over the serial data link. The VMEbus's address bus transfers source and destination address information to a potential receiving node. The AutoBahn then transfers data over the serial bus to the node in blocks, which must start on a 32-byte boundary.

A simplex connection, which transfers 1-way data point-to-point, is the easiest transfer method and lets systems transfer large blocks of graphics data. A duplex configuration containing multiple parties on the bus is more complicated. In this configuration, the VMEbus must establish a bus master and slave during arbitration. If a channel is busy, the slave must notify the requester that the slave cannot comply with the request.

On 3U VMEbus cards, the only line available to signal a busy channel is the bus-error (BERR) line. However, the use of BERR as a notification line creates a problem: It signals that a serious error has occurred in the VME system. To use BERR, system software must be able to discover if BERR is signaling a serious system failure or a busy channel. Because of this drawback, designers are considering other notification methods, such as semaphores and token passing.

Although PEP developed AutoBahn to give 3U VMEbus boards a midlife spark, 6U VMEbus implementations provide a wider range of possibilities. A 6U implementation can use the RETRY line on the P2 connector to notify a busy signal instead of the BERR line. The RETRY line requires less software work. In addition, designers can construct multiple AutoBahn serial buses on the undefined pins of rows A and C of the P2 connector to create multichannel architectures.

Until August 1994, AutoBahn Spanceivers will be available through the AutoBahn Consortium. Thereafter, all Spanceiver sales will be through Motorola Semiconductor. Membership in the AutoBahn Consortium gives you early access to five first-run production Spanceivers during the second quarter of 1994 for $30,000. Executive members can purchase additional Spanceivers for $250 each in small quantities.

Cable and backplane standard

One more avenue designers are exploring to increase parallel-bus bandwidth is the P1394 standard, another high-speed serial bus. A committee within the IEEE is currently developing the P1394 standard. Based on Apple Computer's FireWire technology, the P1394 standard defines a hierarchical bus topology comprising serial backplane buses that connect to a cable medium via bus bridges. The serial backplane buses provide a low-cost alternative for parallel backplane buses, and the cable medium interconnects modules on different backplanes.

The cable medium allows 16 physical connections, each as long as 4.5m. Using the cable medium in node-branching and daisy-chaining topologies enables the connection of workstations, hard-disk drives, printers, cameras, CD-ROMs, and scanners. An inexpensive multiconductor cable employs six shielded, twisted-pair wires. The cable dedicates two differential lines for data and two as a strobe line. The other two lines are 8 to 40V-dc power lines having 1.5A capacity for driving the physical layer of each node. This method lets you insert live cables onto the bus without damaging the network.

P1394 transmits data at 98.304, 196.608, and 393.216 Mbps over the cable medium. All higher speeds must be backward-compatible with lower speeds. Backplanes, which can have as many as 63 nodes, have data rates that depend on the logic circuitry employed. A TTL serial backplane bus transfers data at 24.576 Mbps, and a backplane-transceiver-logic (BTL) or ECL serial backplane transfers data at 49.152 Mbps. The bus bridge that connects a backplane to the cable medium must accommodate the rate differences.

Unlike AutoBahn, the P1394 standard provides arbitration and source and destination information directly over the serial bus. The bus automatically assigns node addresses, removing the requirement for ID switches. The standard also defines a transmission protocol comprising three stacked layers and a serial bus-management function that employs IEEE-1212-compatible control and status registers.

Protocols describe transfers

In the P1394, a software-transaction layer defines a request-response protocol to perform the bus transaction. A link layer provides a confirmation of reception to the transaction layer and provides addressing data checking and data framing. The physical layer translates the logical symbols used by the link layer into electrical signals on the serial bus media.

The transmission protocol adds header information to data packets on the serial bus. The protocol allows for direct transactions, lock subcommands, and split transactions on the bus. The bus can transmit data asynchronously or isochronously. Isochronous-data transmission occurs at regular intervals to guarantee a fixed latency for real-time applications, such as multimedia. Texas Instruments has a licensing agreement with Apple Computer to develop a 2-chip set for the link and physical layers of the P1394 standard. That chip set should be available in the second quarter of 1994.

Gaps separate each data packet on the serial bus, giving each node an opportunity to arbitrate for the bus. Isochronous access has highest priority, and a fair arbitration protocol prevents any node from monopolizing the entire asynchronous bandwidth of the bus. In addition, the protocol can give urgent access to nodes operating on a backplane serial bus. Draft copies of the P1394 standard are available from the IEEE Computer Society, 1730 Massachusetts Ave NW, Washington, DC 20036, or phone (202) 371-0101.

Moving up the performance curve is the Fibre Channel. The ANSI X3T9.3 committee chartered the Fibre Channel working group in 1988 to develop an interconnection standard for bidirectional point-to-point serial data communications between workstations, mass-storage subsystems, and peripherals. The requirements are ambitious. The Fibre Channel transfers data at 133 to 1062 Mbps on a single fiber over distances as long as 10 km. Because information can flow in both directions simultaneously, users can transmit on one fiber and separately receive data on another fiber.

The Fibre Channel's interconnection fabric operates similarly to that of a switched telephone exchange, where a user dials an address (node) and connects to another address (node) on the fabric. The fabric uses crosspoint switches to provide a choice of multiple paths between nodes. Fibre Channel allows 16 million nodes on a single fabric, whereas a SCSI parallel bus allows only 16 nodes that must be within feet of each other.

Transmission over the Fibre Channel is isolated from the control protocol, so that users can implement different topologies, such as point-to-point links, rings, multidrop buses, and crosspoint switches. Whether the fabric is a circuit switch, an active hub, or a loop is irrelevant because the fabric, not the Fibre Channel node, is responsible for the topology's station management.

The Fibre Channel defines a multilayer stack of protocols, not unlike network protocols, but not conforming directly to OSI layers. The Fibre Channel Physical (FC-PH) standard comprises three lower levels: FC-0, FC-1, and FC-2. The lowest layer, FC-0, specifies the physical characteristics of the media, transmitters, receivers, and connectors. The media can be fiber optics for high-speed long ranges or copper for lower-speed shorter ranges. FC-1 defines an 8B/10B encoding/ decoding scheme in which 10 bits represent 8 bits of real data. IBM has a patent on the scheme, and the 25% overhead of using 10 bits of transmission to transfer 8 bits of data causes a maximum transfer rate of 100 Mbytes/sec (200 Mbytes for 2-way transmission) at 1062 Mbps.

FC-2 defines the Fibre Channel's transport mechanism. This layer manages rules for placing data, frame headers, cyclic-redundancy-check error detection, and frame delimiters into packets for Fibre Channel's packet-switched services. Because Fibre Channel is hardware-intensive, it relies on the frame header to trigger actions. At 1062 Mbps, the Fibre Channel cannot make decisions in microcode fast enough. Fibre Channel also puts no limit on the size of transfers between applications.

The ANSI working group is still developing two upper layers for Fibre Channel. The FC-3 layer will provide common services, such as striping to achieve higher bandwidths and multicasting to deliver a single transmission to multiple destinations. FC-4 will provide a seamless integration to other data-communication protocols, such as asynchrounous-transfer mode (ATM), Fiber Data Distributed Interface (FDDI), High-Performance Parallel Interface (HIPPI), SCSI-3, Ethernet, Token Ring, and the Transfer Control Protocol/Internet Protocol (TCP/IP), to communicate directly over Fibre Channel.

To accommodate a wide range of communications needs, Fibre Channel defines three classes of service. Unlike with FDDI or other ring-type LANs, each class can use as few as two nodes on the fabric. Class 1 is a circuit-switched, dedicated, physical channel. When a host and a peripheral use Class 1 to connect, they make their connection path unavailable to other hosts or peripherals. As a result, Class 1 has the nickname Òselfish modeÓ and is an ideal method to use when the time to make a connection is short or data transmissions are long.

Class 2 is a connectionless, frame-switched link, which provides guaranteed packet delivery with an acknowledgement on receipt. If Class 2 cannot make the delivery due to congestion, it gives the sender a busy signal and immediately tries again. Similar to traditional packet-switched systems, Class 2 systems do not have a dedicated path between two devices, providing a wider-link bandwidth.

Class 2 service is ideal for data transfers to shared mass-storage systems that are some distance from several workstations. An optional Intermix mode reserves a dedicated Class 1 connection but also allows connectionless traffic to share the link if there is available bandwidth.

Class 3 is a connectionless service, similar to Class 2, that sends data to multiple devices attached to the fabric but does not confirm receipt. The transfer, or datagram, is most practical when the time to make a connection is short. Class 3 service is useful for real-time broadcasts, in which timeliness is key, and information not received has little value.

Distance is the greatest factor influencing connection time. It takes an electrical signal about 10 msec to travel 3 km. To establish a logical connection for Class 2 service requires a signal to make a round trip of 20 msec before transfer can begin, whereas Class 3 service can make the connection in 10 msec.

For designers interested in developing Fibre Channel nodes, Applied Micro Circuits Corp offers a Fibre Channel chip set to perform high-speed serial data transmission over fiber-optic or coaxial cable. The interfaces conform to the ANSI X3T9.3 Fibre Channel specification. The S2039 and S2040 transmitter pairs cost from $78 to $225 (1000).