From: Richard Steven Walz X-Mailer: SCO OpenServer Mail Release 5.0 To: ih@doc.ic.ac.uk Subject: Re: Why no mention ... Date: Thu, 17 Oct 96 1:36:11 PDT Message-ID: <9610170136.aa29755@deepthought.armory.com> Dear Ian, Thanks for your response. I did notice that in regard to the control outputs, that you make mention that inputs to them would be "ORed" with current latch outputs, and while the open-collector "wired-negative logic-OR" also called the "wired AND" can be done and is the form of input I was speaking of, this ONLY occurs if the output pinsockets are controlled to be voltage HI by bits such that 04h is outputted to the base + 2 I/O-port. Otherwise exists the most definite problem of actual output state contention and the actual *SHORTING* of external input HI to an internally controlled output LO, resulting in an overheated sink to ground transistor in the open-collector control output line on any of the control lines thus affected! As you might imagine, this is NOT good at all! If it is always the case of an internally controlled HI PULLED-UP output being pulled LO by an external LO input, there is not a problem, as in the mode of using the four control outputs for inputs if they have been set Voltage-HI internally under program control. Read-back will then read a specific state, but with any of the controlled outputs being LO, already having their pull-ups pulled down to ground, additional HI input over- whelms the LO state and might be read in the forbidden region of voltage, and thus give erroneous read-back upon attempt!! This is also a shorted condition causing excessive heating of the open-collector-output buffer sink transistor. I am sorry to have to be bearer of such tidings but do note your wording and my notations below for your benefit: Take good care, -Steve -- -Steve Walz rstevew@armory.com http://www.armory.com/~rstevew/ -Lots of New FTP Electronics Stuff!! 600 Files/37 Dirs (Full Mirror ==> *) -Steve Walz rstevew@armory.com ftp://ftp.armory.com:/pub/user/rstevew * Europe:(Italy) ftp://ftp.cised.unina.it:/pub/electronics/ftp.armory.com * Oz: (Australia) ftp://gold.apana.org.au:/pub/electronics/ftp.armory.com * (U.Cinci) ftp://ieee.cas.uc.edu:/pub/electronics/mirrors/ftp.armory.com * -- --------------------note carefully below---------------------------------- IBM-PC Parallel Printer Port Programming Considerations The printer adapter responds to five I/O instructions: two output and three input. The output instructions transfer data into two latches whose outputs are presented on the pins of a 25-pin D-type female connector. Two of the three input instructions allow the processor to read back the contents of the two latches. The third allows the processor to read the realtime status of a group of pins on the connector. A description of each instruction follows [snipped for brevity only] Input from address 278/378/3BC Hex This command presents the processor with data present on the pins associated with the corresponding output address. This should normally reflect the exact value that was last written. If an external device should be driving data on these pins (in violation of usage groundrules) at the time of an input, this data will be ORed with the latch contents. ***Ian, please note: Note: Actually it will NOT be ORed in any fashion here, but will result in an invalid or forbidden state, depending on its impedance. People have tried using this as a mode of input with bad hardware result for a long time. It seems to work for a minute or a day or even a few weeks, but degrades and causes break-down of the 74LS374 octal latch typically used for this. Also, if the inputs are NOT powerful enough to damage the 74LS374, it is also true that the inputted data will be erroneous!! Thus, as your previous warning stated, this is a violation of the usage groundrules, as well as being electronically preposterous. Sorry, but true. If only they had made this port open collector we would have a chance, but that would slow this port down a bit. A pulled-up output cannot rise out of sink-saturation as fast as one having an active pull-up transistor to overcome its state and capacitance. -Steve Walz rstevew@armory.com *** Input from address 279/379/3BD Hex This command presents realtime status to the processor from the pins as follows. Bit 7 6 5 4 3 2 1 0 Pin 11 10 12 13 15 - - - ***Ian, please note: You have neglected to remark upon bit 7 from pin 11 BUSY being inverted and needing a tilde character to signify it as with the control port bits. It inverts any "1" logical state as received by the program from the voltage LO or "0" voltage presented to its pin 11, and vice versa!! This was a start-up necessity to prevent printers from printing gibberish at power on. Buffers most typically assert 0 outputs at power on, thus once passed through an inverter, that speaks "I'm BUSY" from the printer. -Steve Walz rstevew@armory.com *** Input from address 27A/37A/3BE Hex This instruction causes the data present on pins 1, 14, 16, 17 and the IRQ bit to be read by the processor. In the absence of external drive applied to these pins, data read by the processor will exactly match data last written to the corresponding output address in the same bit positions. Note that data bits 0-2 are not included. If external drivers are dotted to these pins, that data will be ORed with data applied to the pins by the output latch. ***Ian, please note: Here it will work as input, ONLY IF the voltage state is one of being pulled voltage-HI at the output pinsockets by the program control output of 04h to this port, necessary to output a logical 00000100 because the lower four are logically inverted from their pin voltage consequence, EXCEPT for bit 2, the 4's bit. Thus, this pulls all four control pins voltage HI, perfect for inputting, and leaves the interrupt (bit 4) turned off, as well as bit 5 if this is a possible so-called bi-directional Byte Mode port, as bit 5 is the last to control the data port to be input if it is logical "1" enabled! Still the statement that this has ANYTHING to do with OR is quite mistaken! And again, sorry to be the bearer of such critical tidings. I recommend my new lptskmtx.* series of ASCII-matics in my web/ftp site's LPT/ subdir. They are being found most instructive as to the SPP port's original properties and the reason for them in schematic. -Steve Walz rstevew@armory.com *** Bit 7 6 5 4 3 2 1 0 Pin - - - IRQ ~17 16 ~14 ~1 enable state assumed after processor reset 0 1 0 1 1 _________________________________________________________________ [ Previous ] [ Index ] [ Next ] _________________________________________________________________