June 5, 1997

Provide ESD protection for I/O ports

Brett Fox and Pirooz Parvarandeh, Maxim Integrated Products

ESD causes many problems: It not only damages equipment, but also makes equipment difficult to sell because of stringent performance standards. Fortunately, you can take steps to ensure the safety of some of the most vulnerable components, the interface ICs.

ESD can threaten an electronic system when someone replaces a cable or even touches an I/O port. Discharges that accompany these routine events can disable the port by destroying one or more of its interface ICs (Figure 1). Such failures can also be costly: They raise the price of warranty repairs and diminish the product's perceived quality.

ESD causes trouble in another way, too. Since January 1997, the European Union has barred manufacturers from selling products to Europe unless the equipment meets minimum levels of ESD performance. These two factors, in addition to the increasing amount of electrical communication between computers and computer-related equipment, emphasize the need for engineers to understand ESD. A proper understanding of ESD requires an awareness of not only the voltage levels involved, but also the voltage and current waveforms, IC-protection structures, test methods, and application circuits.

ESD occurs when two dissimilar materials come together, transfer charge, and move apart, producing a voltage between them. Walking on a rug with leather soles, for example, can generate voltages as high as 25 kV. The level of induced electrostatic voltage depends on the relative charge affinity between the rug and the shoe leather, the humidity, and other factors.

The triboelectric series describes this charge affinity between various materials (Table 1). Charge transfer occurs when any two items on the list come into contact. Materials higher in the series acquire positive charge, and materials lower in the series acquire negative charge. The net charge and resulting electrostatic voltage are greater for items farther apart on the list.

ESD susceptibility

Two common methods test the ESD susceptibility of ICs. The oldest, MIL-STD-883 method 3015.7, serves primarily as an aid to understanding the precautions necessary for packaging and handling ICs. This method tests each package pin against other groups of pins and classifies the device according to the lowest voltage for which failure occurs.

The applied signal in this test is a current waveform that derives from a circuit called the human-body model, which simulates the typical capacitance and source impedance of a human body (Figure 2). Circuit layout is critical because the actual waveform delivered to the IC also depends on parasitic inductance and capacitance associated with the test connections and pc board. The resulting current waveform represents the ESD that occurs when a person touches an object, such as an IC.

The other common ESD-testing method, IC-121, was developed by the Electronic Industries Association of Japan (EIAJ) and differs from 3015.7 only in the values for R and C. Based on a circuit called the machine model, also in Figure 2, this method applies a current waveform similar to that produced when an IC makes contact with its handling machinery. By mimicking the ESD events that result when charges accumulate on moving parts, the waveform simulates static discharges that can happen during machine assembly.

The two methods are complementary, so you shouldn't choose one over the other. Because ESD can affect ICs during manufacturing and pc-board assembly, as well as after the end product goes into service, a test based on both the human-body and the machine models provides adequate assurance of the IC's tolerance for the rigors of manufacturing and insertion.

Some ICs, whose pins are exposed to the outside world through connectors, can encounter ESD even when mounted on a pc board within an enclosure. ESD exposure is less likely for the other pins, which connect to circuitry on the board. For this class of IC, a test method such as 3015.7, which tests pin combinations, provides an inadequate representation of ESD susceptibility for the I/O pins.

Both methods offer ratings according to the lowest voltage failure on any pin. This approach might not do justice to the higher levels of internal ESD protection that the I/O pins require and that some manufacturers provide. A device might have I/O pins that withstand ±15 kV, for example, and non-I/O pins that fail at ±2 kV. Using the above methods, the device's ESD rating would be less than ±2 kV. Fortunately, however, better test methods are now available for rating the I/O pins.

New ESD tests for I/O ports

An I/O port allows communication with other pieces of equipment. I/O ports for ICs comprise logical groups of pins that give access to equipment external to the system that contains the IC. These pins are subject to static discharge and other abuse as operators connect and disconnect cables from the system. For the I/O pins of an RS-232C- or RS-485-interface IC, an ideal test method for ESD susceptibility should

• Test the I/O pins only in ways that simulate exposure to ESD events in actual equipment;

• Apply test waveforms that model ESD that the human body produces. Different circuit models specify different amplitudes, rise and fall times, and transferred power;

• Test the IC with and without applying power; and

• Define IC failures to include latch-up (a momentary loss of operation) as well as catastrophic or parametric failure. Latch-up is a failure mechanism because it can lead to reliability problems and system malfunctions if you do not detect it.

Equipment manufacturers are increasingly using two new methods that comply with these four requirements to test the ESD susceptibility of I/O ports. The first method is a modification of MIL-STD-883 method 3015.7. It uses the same circuit model and waveform as the original method but applies ESD pulses only to the I/O pins of a device. The intent is to simulate the fault currents that an IC installed on a board and operating in the target system is exposed to. The test circuit generates the test waveform using the same component values that 3015.7 originally specified (Figure 3).

Like the original 3015.7, the modified method defines only an ESD waveform and the criteria for failure; after exposure to the waveform, a failed IC must either exhibit latch-up or fail one or more data-sheet specifications. The modified method stipulates no operating mode for the IC during test, but you should exercise all possible modes of operation: power on/off, transmitter outputs high/low, standby/normal operation, etc.

Similarly, the modified 3015.7 does not compel products to withstand particular levels of ESD but only defines classes of protection. New transceivers, however, such as Maxim's RS-232C MAX213E and MAX3185 and RS-485 MAX487E, provide protection levels to ±15 kV. This level allows some users to eliminate costly TransZorbs (General Semiconductor Inc, Tempe, AZ) and other external protection circuitry.

IEC 1000-4-2 model is more exacting

The second, more stringent method for testing ICs that include I/O pins is IEC 1000-4-2. The International Electrotechnical Commission developed this equipment-level test as an acceptance condition for equipment destined for sale in Europe, but this method is rapidly gaining acceptance as a standard ESD criterion in the United States and Japan as well. Though not originally an IC specification, this method now does extra duty as an ESD test for ICs. Like the modified 3015.7, this method tests only the I/O pins.

The model for IEC 1000-4-2 is again the circuit in Figure 2 but with different component values. R₂ represents a human holding a screwdriver or other metallic object, and C₁ represents an estimate of human-body capacitance. This circuit produces a current waveform with a steeper rise time than 3015.7 produces (Figure 4).

IEC 1000-4-2 specifies ESD testing for both contact and air discharge. ESD events that actual contact causes are more repeatable but less realistic. Air discharge is more realistic but subject to wide differences in waveform shape, according to variations in temperature, humidity, barometric pressure, distance between the IC and the electrode, and the rate of approach to the IC pin. Any change in waveform shape can significantly affect the measured level of tolerance for ESD.

IEC 1000-4-2 defines four levels of compliance that correspond to the lowest maximum voltage the I/O pins can withstand (Table 2). The table defines these levels for both contact and air discharge.

Choose contact or air discharge

Testing ICs for ESD ruggedness with IEC 1000-4-2 requires an ESD gun, which allows testing with either contact or air discharge. Contact discharge requires physical contact between the gun and the I/O pin, by a switch internal to the gun, before you apply the test voltage. Air discharge requires charging the gun with the test voltage before the gun approaches the I/O pin (from the perpendicular and as fast as possible). The air-discharge test produces a spark at some critical distance from the test unit.

ESD that air discharge produces resembles actual ESD. But, like actual ESD, the air-discharge variety is hard to duplicate. The amount of air-discharge ESD depends on many variables that are hard to control. Thus, attesting to the general importance of repeatability in testing, IEC 1000-4-2 recommends contact discharge, and the modified 3015.7 requires only contact discharge. In either case, the test procedure calls for at least 10 discharges at each test level.

The main difference between the modified 3015.7 and the air- or contact-discharge version of IEC 1000-4-2 is the peak currents each method produces in the device under test. Different component values can cause these peak currents to differ by a factor greater than five (Table 3). Because peak currents produce the unwanted power that an IC must dissipate, IEC 1000-4-2 usually is the more demanding test method for ESD.

High current can damage an IC in various ways, including excessive local heating, melted silicon, spiked junctions caused by a short that dissolves aluminum in the silicon (Figure 5), damaged metal lines, gate-oxide failure due to excessive voltage, and transistor damage due to electrothermal migration (Figure 6).

Apply the appropriate protection

To protect against ESD, you can either add the protection externally or choose ICs with high levels of protection built- in. External protection circuitry includes metal-oxide varistors and silicon avalanche suppressors, such as TransZorbs. These devices are effective but expensive: Silicon avalanche protectors cost as much as $0.30/line. External ESD protection also consumes valuable board area and adds capacitance to the I/O line. To overcome these limitations, manufacturers have repeatedly raised the level of ESD protection in their ICs. Maxim, for example, now provides ±15-kV protection for RS-232C ICs whether tested in accordance with IEC 1000-4-2 or the human-body model.

An ESD-current waveform consists of extremely fast rise times, so the circuit's distributed parasitic impedances strongly affect the waveform's progress through an IC. Therefore, attention to the external layout ensures maximum performance by the IC's internal protection networks. With its interface ICs, Maxim recommends that you follow standard analog-layout techniques (placing all bypass and charge-pump capacitors as close as possible to the IC), include a ground plane on the pc board, minimize trace inductance and capacitance, and place the IC as close as possible to the I/O port.

To characterize an RS-232C transceiver or other interface IC for reliability in the presence of ESD, Maxim recommends using the modified 3015.7 and the IEC 1000-4-2 model as well, following a similar procedure in each case. Step through the specified ESD range in increments of 200V and, at each level, zap the device 10 times with each polarity of voltage, approximately once per second.

Because the intent of these tests is to assess the ESD performance of an IC installed in end equipment, the test setup should cause ESD currents to flow along the same paths as they would in that equipment. You should administer zaps with respect to the IC's ground pin. As IEC 1000-4-2 states, circuit ground usually connects to the equipment chassis. Maxim recommends the model NSG 435 ESD gun by Schaffner Instruments (Luterbach, Switzerland) for the IEC 1000-4-2 method and the model 4000 ESD tester by IMCS (a division of Oryx Technology Corp, Fremont, CA) for the modified 3015.7 method.

You should check for failures by monitoring three parameters after each zap. First, the supply current should remain constant--an increase may indicate latch-up or internal damage. Second, the transmitter output voltage should continue to meet the ±5V minimum levels for RS-232C transmission. Third, the receiver input resistance should remain 3 to 7 kilohms and, ideally, at a constant level. Be sure to zap and test the device in all its modes, including normal operation, shutdown, power off, and transmitter high/low.

Reference

1. Electrostatic Discharge, Protection Test Handbook, Second Edition, KeyTek Instrument Corp, 1986, pg 7.

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